DSP56311EVM【PDF 234/360 页】KIT EVALUATION FOR DSP56311

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Triple Timer Module

Table 9-3. Timer Control/Status Register (TCSR) Bit Definitions (Continued)

Bit Number

7–4

Bit Name

TC[3–0]

Reset Value

0

Timer Control

Description

Control the source of the timer clock, the behavior of the TIO signal, and the

Timer mode of operation. Section 9.3 , Operating Modes, on page 9-5

describes the timer operating modes in detail. To ensure proper operation,

the TC[3–0] bits should be changed only when the timer is disabled (that is,

when the TCSR[TE] bit is cleared).

Note:

If the clock is external, the counter is incremented by the transitions

on the TIO signal. The external clock is internally synchronized to

the internal clock, and its frequency should be lower than the

internal operating frequency divided by 4 (that is, CLK/4).

Bit Settings

Mode Characteristics

TC3

0

TC2

0

TC1

0

TC0

0

Mode

Number

0

Mode

Function

Timer and

TIO

GPIO

Clock

Internal

GPIO

1

0

0

0

1

1

Timer pulse

Outpu

Internal

t

0

0

1

0

2

Timer toggle

Outpu

Internal

t

0

0

1

1

3

Event counter

Input

Externa

l

0

1

0

0

4

Input width

Input

Internal

measurement

0

1

0

1

5

Input period

Input

Internal

measurement

0

1

1

0

6

Capture

Input

Internal

event

0

1

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

7

8

9

10

11

12

13

14

15

Pulse width

modulation

Reserved

Watchdog

pulse

Watchdog

Toggle

Reserved

Reserved

Reserved

Reserved

Reserved

Outpu

t

—

Outpu

t

Outpu

t

—

—

—

—

—

Internal

—

Internal

Internal

—

—

—

—

—

Note:

The GPIO function is enabled only if all of the TC[3–0] bits are 0.

9-26

3

0

Reserved. Write to zero for future compatibility.

DSP56311 User’s Manual, Rev. 2

Freescale Semiconductor

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